EPM7160STC100-10N

programmable logic device, qfp, –25 to 25 mA

Rated 5 Rating 5 | reviews | Write a review

Price:: US $21.00~43.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $21.00~43.00

PartNumber:: EPM7160STC100-10N

Brand:: Altera Corporation - ALTR | Pack: QFP | D/C: 07+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. Sunny's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2011-07-21

From Other Seller

Part Number:EPM7160STC100-10N
US $21.00 - 43.00
ECA1HHG4R7

US $10.00 - 10.00 / Piece
(0) Remove
HT46R47

US $0.35 - 1.50 / Piece
(0) Remove
Quantity:

piece

Product Summary

The EPM7160STC100-10N is a programmable logic device. The EPM7160STC100-10N high-density, high-performance PLDs is based on Altera second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification.

Parametrics

EPM7160STC100-10N absolute maximum ratings: (1)IOUT DC output current, per pin –25 25 mA; (2)TSTG Storage temperature No bias –65 150℃; (3)TAMB Ambient temperature Under bias –65 135℃; (4)TJ Junction temperature Ceramic packages, under bias 150℃; (5)Ceramic packages, under bias 150℃; (6)PQFP and RQFP packages, under bias 135℃.

Features

EPM7160STC100-10N features: (1)High-performance, EEPROM-based programmable logic devices; (2)(PLDs) based on second-generation MAXR architecture; (3)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices ISP circuitry compatible with IEEE Std. 1532 Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (7)PCI-compliant devices available.